Description
Important: Hermes is currently supported by the encompassing environment called ATLAS. Please, if you are interested in Hermes or Maia, see also the ATLAS homepage here. Atlas is a software allowing the automatic generation of the HERMES and other NoCs developed by our Research Group.
HERMES is an infra-structure used to generate NoCs with packet switching adaptable for different topologies, flit sizes, buffer depths and routing algorithms. The HERMES denomination is also employed to refer to the NoCs implemented with this infrastructure and to the other components of this network, like routers and buffers. With the HERMES infrastructure it is possible to implement the three lower levels of the ISO OSI Reference Model: (i) physical - corresponding to the definition of the router physical wiring interface; (ii) link - which defines the data transfer protocol between routers. The HERMES infrastructure adopts an explicit handshake protocol for sending and receiving data reliably; (iii) network - corresponding to the level where the switching mode employed by the NoC is defined. The HERMES infrastructure assumes this to be wormhole packet switching. The main component that implements this characteristic is the HERMES router. This router contains two parts: a control logic and a set of up to 5 bidirectional ports: East, West, North, South and Local. Each port contains a queue to temporarily store packet flits, and which size is parameterizable at design time. The Local port establishes the communication path between the processing core and the NoC, and from this later to any other core in the system. The remaining ports connect routers among them. The control logic is composed by two modules: routing and arbitration. The routing module implements one of the algorithms made available by the HERMES infra-structure. The arbitration module determines which packet must receive priority to be switched inside the router, when more than one packet arrive simultaneously at the router requiring the same output port. A dynamic arbitration scheme is assumed by the HERMES infra-structure.
HERMES Router External Interface
Pin
Orientation
Size
Type
Description
tx
Out
1
std_logic
control
signal indicating the existence of data available at the output of the
router.
data_out
Out
16
std_logic_vector
contains the data
available at the output of the router.
ack_tx
In
1
std_logic
control
signal indicating to the router that the available data has been
received by the next router.
rx
In
1
std_logic
control
signal indicating the existence of data available at the input of the
router.
data_in
In
16
std_logic_vector
contains the data available at the input of the
router.
ack_rx
Out
1
std_logic
control
signal indicating to the next router that data has been received by this
router.
Download
| Version | Access | File | Description |
| V1000_TC
- 29/03/2004 HERMES NoC Version - from the End of Term work (see below), developed for XC2V1000 Virtex2 Xilinx FPGA. NoC implementation with 2x2 mesh topology and 8-bit flit size. The system is composed by three R8 processor cores and one RS-232 serial interface controller. |
Public | Mesh2x2_3p.zip | Zip containing the VHDL description of the HERMES NoC and of the processing cores (R8 processor, memory and serial interface controller). |
| V800_TC
- 29/03/2004 HERMES NoC Version - from the End of Term work (see below), developed for XCV800 Virtex Xilinx FPGA. NoC implementation with 2x2 mesh topology and 8-bit flit size. The system is composed by three R8 processor cores and one RS-232 serial interface controller. |
Public | mesh2x2_3p.zip | Zip containing the VHDL description of the HERMES NoC and of the processing cores (R8 processor, memory and serial interface controller). |
| TURBO
- 29/03/2004 Version resulting from the unification of the arbitration and routing modules within the HERMES router, reducing the total routing time. Important observation: The NoC packets in this version are composed by: 1 flit [source|target] + 1 flit [size] + 2 ^ flitsize [payload]. |
Public | mesh5x5_turbo.zip | Contains the VHDL description of the NoC with 5x5 mesh topology, using 16-bit flit size and input queue depth equal to 8 flits. |
| Public | HermesTurbo.doc | Description and evaluation of the modifications conducted at the HERMES NoC to reducing the routing time. |
This page was last updated on January 15th, 2008.
Contact
Designer:
Aline Vieira de Mello / Leandro Heleno Möller
E-mail:
alinev@inf.pucrs.br /
moller@inf.pucrs.br
Contact people:
Ney Laert Vilar Calazans / Fernando Gehm Moraes
E-mail:
calazans@inf.pucrs.br /
moraes@inf.pucrs.br
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to
or to
We will fix it in the shortest possible delay. Thanks for your help!